There are a variety of electrical systems which require one or more sources of power for controlling the operation of a system application device. As a non-limiting example, a liquid crystal display (LCD), such as that employed in desktop and laptop computers, or in larger display applications such as large scale television screens, requires an associated set of high AC voltage-driven cold cathode fluorescent lamps (CCFLs) or other light sources mounted directly behind it for backlighting purposes. Indeed, large LCD panels require relatively large numbers (e.g., on the order of ten to forty) of such lamps for uniform backlighting.
Adjusting the brightness (or dimming) of a CCFL is customarily effected by means of a pulse width modulation (PWM) dimming signal, which controllably switches the lamp drive voltage and current off for brief periods of time; namely, the CCFL is turned ON and OFF for relatively short periods of time (e.g., from 0.1 to 5 msec. each), with the brightness of the lamp being proportional to the PWM signal's duty cycle. This methodology may be carried out by applying a separate PWM dimming signal to each inverter.
In order to properly establish the duty cycle of the PWM dimming signal, the optical output of the CCFL is monitored to measure the average brightness of the lamp over a plurality of cycles of the PWM signal. For this purpose, an analog light sensor is optically coupled to sense the light output of the CCFL, and the output of the light sensor, the amplitude of which varies in accordance with the PWM signal being applied to the CCFL, is subjected to an integration process which yields an output that ostensibly represents the average brightness of the lamp. Where the light sensor PWM output signal is converted into digital format for downstream processing, it is necessary that the digitization process be conducted over a plurality of cycles of the optical detector's output signal in order to realize an ‘average’ of the brightness of the lamp. An undesirable ‘flickering’ problem may occur if the integration period of the analog-to-digital conversion is selected arbitrarily, with no consideration being given to whether or not the integration period is synchronized with a prescribed multiple of the period of the PWM signal produced by the optical sensor.
This problem may be readily understood by reference to the waveform diagram of FIG. 1, which shows a fixed duty cycle PWM ‘input’ signal 100, as may be produced from the output of an optical sensor monitoring the modulation of the light output of the CCFL. Beginning with the assertion of a first measurement interval reset pulse 100-1 in the top line of FIG. 1, then during each of three sequential ‘high’ amplitude intervals 111-1, 111-2 and 111-3 of the PWM signal 110 following this reset pulse, the contents of a counter/integrator within an analog-to-digital converter are incremented by a prescribed clock signal applied thereto. During each ‘low’ (or zero) amplitude interval 112-1 and 112-2 of the PWM signal 110, the contents of the integrator remain unchanged. Eventually, at the end of the measurement interval, which is just prior to the second measurement interval reset pulse 100-2, the counter/integrator output will be at some value 121. For the illustrated example, this value is based upon the sequential incrementing of a counter during the three ‘high’ amplitude pulses 111-1, 111-2 and 111-3. Upon the assertion of the second measurement interval reset pulse 100-2, the value 121 of the integrator/counter is latched in light output monitoring and control circuitry for the next measurement interval, and the contents of the integrator/counter are then cleared.
Then, beginning with the assertion of the next succeeding measurement interval reset signal 100-2, during each of two ‘high’ amplitude interval 111-4 and 111-5 of the PWM signal 110, the contents 120 of the counter/integrator are sequentially incremented—eventually reaching a value 122, just prior to the next reset pulse 100-3. As can be seen from FIG. 1, because only two ‘high’ amplitude intervals are integrated during the integration period between measurement interval reset pulses 100-2 and 100-3, the integration value 122 will be less than the integration value 121. This means that upon assertion of the next reset signal 100-3, the relatively reduced value 122 of the integrator will be latched in the light output monitoring and control circuitry for the next measurement interval.
As will be appreciated from the foregoing description and as can be seen from FIG. 1, because the above described operations are sequentially repeated for successive integration periods, the latched values will alternately change between a relatively higher value 121 and a relatively lower value 122, even though the average value of the input signal 110 itself does not change (in the absence of a change its duty cycle). This alternating of the latched value constitutes the aforementioned unwanted ‘flickering’ of the average light value output of the lamp.